T-EMU 2

A high performance micro-processor emulator.
Performance of up to 110 MIPS on a modern machine.
Created by TERMA.

Introduction

T-EMU 2 is an advanced micro processor emulator, currently targeted at emulating common processors and devices used in European spacecraft. The emulator is fully capable of emulating multi-core processors.

Based on the LLVM framework T-EMU 2 is a high performance emulator (currently providing 110 MIPS on a 3.5GHz PC when running Dhrystone). Currently supported instruction set architectures include the SPARCv8 (with some extensions used in the supported processors). Other architectures can be made available if requested.

The following processors are available in T-EMU 2:

  • ERC32 and MEC device models
  • LEON2 with on-chip devices
  • LEON3 and LEON4 with fundamental GRLIB devices

Note that the emulator is not limited to the mentioned processors and device models. The emulator is very flexible. Additional CPU cores can be added if requested and additional device models can be implemented by the emulator user, or by Terma.

Download the T-EMU Flyer

Papers and Talks

  • T-EMU Evolution (SESP 2015): paper, slides
  • Emulator Performance Analysis (SESP 2015): paper, poster
  • T-EMU: The Next Generation Micro-Processor Emulator (EuroLLVM April 13-14, 2015): slides
  • High Performance Microprocessor Emulation for Software Validation Facilities and Operational Simulators (SpaceOps 2016): paper, slides

Training

On-site training can be arranged.
Training sessions will be performed by experienced lecturers.
For additional information, please contact us.