T-EMU 2 is an advanced micro processor emulator, currently targeted at emulating common processors and devices used in European spacecraft. The emulator is fully capable of emulating multi-core processors.
Based on the LLVM framework T-EMU 2 is a high performance emulator (currently providing 110 MIPS on a 3.5GHz PC when running Dhrystone). Currently supported instruction set architectures include the SPARCv8 (with some extensions used in the supported processors). Other architectures can be made available if requested.
The following processors are available in T-EMU 2:
Note that the emulator is not limited to the mentioned processors and device models. The emulator is very flexible. Additional CPU cores can be added if requested and additional device models can be implemented by the emulator user, or by Terma.
On-site training can be arranged. Training sessions will be performed by experienced lecturers. For additional information, please contact us.